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74AC02*74ACT02 Quad 2-Input NOR Gate
November 1988 Revised February 2005
74AC02*74ACT02 Quad 2-Input NOR Gate
General Description
The AC02/ACT02 contains four, 2-input NOR gates.
Features
s ICC reduced by 50% on 74AC02 only s Outputs source/sink 24 mA s ACT02 has TTL-compatible inputs
Ordering Codes:
Order Number 74AC02SC 74AC02SCX_NL 74AC02SJ 74AC02MTC 74AC02PC 74ACT02SC 74ACT02MTC 74ACT02PC Package Number M14A M14A M14D MTC14 N14A M14A MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. (PC not available in Tape and Reel.) Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names An , Bn On Description Inputs Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS009912
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74AC02*74ACT02
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC ) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r50 mA r50 mA 65qC to 150qC
140qC
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate ('V/'t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) Maximum Input Leakage Current IOLD IOHD ICC (Note 5) Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 2.0 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1
V
IOH IOH IOH IOUT
12 mA 24 mA 24 mA (Note 3)
50 PA
V VIN VIL or VIH 12 mA 24 mA 24 mA (Note 3) VCC, GND 1.65V Max 3.85V Min VCC
0.44 0.44 0.44 V
IOL IOL IOL VI
r0.1
r1.0
75
PA
mA mA
VOLD VOHD VIN or GND
75
20.0
PA
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC02*74ACT02
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 7) Maximum Quiescent Supply Current
Note 6: All outputs loaded; thresholds on input associated with output under test. Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
TA Typ 1.5 1.5 1.5 1.5 4.49 5.49
25qC
2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT IOUT VIN V V IOH IOH IOUT VIN
Conditions 0.1V or 0.1V or
VCC 0.1V VCC 0.1V
50 PA
VIL or VIH
24 mA 24 mA (Note 6)
50 PA VIL or VIH
0.001 0.001
0.1 0.1 0.36 0.36
V
IOL 24 mA IOL 24 mA (Note 6) VI VI VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC or GND
5.5 5.5 5.5 5.5 5.5 0.6
r0.1
r1.0
1.5 75
PA
mA mA mA
VOLD VOHD VIN
75
4.0 40.0
PA
AC Electrical Characteristics for AC
VCC Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay (V) (Note 8) 3.3 5.0 3.3 5.0
Note 8: Voltage Range 3.3 is 3.3V r 0.3V Voltage Range 5.0 is 5.0V r 0.5V
TA CL Min 1.5 1.5 1.5 1.5
25qC
50 pF Typ 5.0 4.0 5.0 4.5 Max 7.5 6.0 7.5 6.5
TA
40qC to 85qC
CL 50 pF Max 8.0 6.5 8.0 7.0 ns ns Units
Min 1.0 1.0 1.0 1.0
AC Electrical Characteristics for ACT
VCC Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay (V) (Note 9) 5.0 5.0 Min 1.0 1.0 TA CL
25qC
50 pF Typ 6.0 6.5 Max 8.5 9.5
TA
40qC to 85qC
CL 50 pF Max 9.0 10.0 ns ns Units
Min 1.0 1.0
Note 9: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 30.0 Units pF pF VCC VCC OPEN 5.0V Conditions
3
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74AC02*74ACT02
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
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74AC02*74ACT02
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
5
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74AC02*74ACT02
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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6
74AC02*74ACT02 Quad 2-Input NOR Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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